﻿@techreport{
hls:catapult,
   Title = {Catapult C Synthesis},
   Institution = {Mentor Graphics Corporation, Products Overview, },
      Year = {} }



@techreport{
hls:catapult-use,
   Title = {Pioneer Chooses Mentor Graphics Catapult C Synthesis Tool for Research and Design of Digital Signal Processing Applications},
   Number = {http://www.embedded-computing.com/news/db/?2908},
   Month= {May 23},
      Year = {2006} }



@article{
hls:ADC95,
   Author = {Ahmad, I. and Dhodhi, M. K. and Chen, C. Y. R.},
   Title = {Integrated scheduling, allocation and module selection for design-space exploration in high-level synthesis},
   Journal = { IEE Proceedings on Computers and Digital Techniques,},
   Volume = {142},
   Number = {1},
   Pages = {65-71},
   Note = {1350-2387},
   Abstract = {High-level synthesis consists of many interdependent tasks such as scheduling, allocation and binding. To make efficient use of time and area, functional unit allocation must be performed using a library of modules which contains a variety of module types with identical functionality, but different area and delay characteristics. The synthesis technique presented in the paper simultaneously performs scheduling, allocation and module selection, using problem-space genetic algorithm (PSGA) to produce area and performance optimised designs. The PSGA-based system uses an intelligent design-space exploration technique by combining a genetic algorithm with a simple and fast problem-specific heuristic to search a large design space effectively and efficiently. The efficient exploration of design-space is essential to design cost-effective architectures for problems of VLSI/ULSI complexity. The PSGA method offers several advantages such as the versatility, simplicity, objective independence and the computational advantages for problems of large size over other existing techniques. The proposed synthesis system handles multicycle functional units, chaining, conditional constructs, loops and structural pipelining. Experiments on benchmarks show very promising results},
   Keywords = {circuit CAD
computational complexity
genetic algorithms
high level synthesis
scheduling
VLSI/ULSI complexity
area
benchmarks
chaining
delay
design-space exploration
functional unit allocation
genetic algorithm
high-level synthesis
identical functionality
integrated allocation
integrated scheduling
loops
module selection
multicycle functional unit
problem-space genetic algorithm
structural pipelining
versatility},
   Year = {1995} }



@book{
hls-book4,
   Author = {Camposano, Raul and Wolf, Wayne},
   Title = {High-Level VLSI Synthesis},
   Publisher = {Springer-Verlag New York, LLC},
      Year = {2001} }



@inproceedings{
hls:chau94,
   Author = {Chaudhuri, S. and Walker, R. A.},
   Title = {{ILP-based} scheduling with time and resource constraints in high level synthesis},
   BookTitle = {VLSI Design},
   Pages = {17-20},
   Abstract = {Presents a formal analysis of the constraints of the scheduling problem, and evaluates the structure of the scheduling polytope described by those constraints. Polyhedral theory and duality theory are used to demonstrate that efficient solutions of the scheduling problem can be expected from a carefully formulated integer linear program (ILP). Furthermore, the authors present an algorithm to lower bound the resource requirement of the time-constrained scheduling problem that enables them to solve the ILP more efficiently},
   Keywords = {VLSI
duality (mathematics)
integer programming
logic CAD
resource allocation
scheduling
ILP-based scheduling
duality theory
formal analysis
high level synthesis
integer linear program
polyhedral theory
resource constraints
resource requirement
scheduling polytope
time constraints},
   Year = {1994} }



@inproceedings{
hls:CS02,
   Author = {Chen, Chunhong and Sarrafzadeh, M.},
   Title = {Power-manageable scheduling technique for control dominated high-level synthesis},
   BookTitle = {Design, Automation and Test in Europe },
   Pages = {1016-1020},
   Abstract = {Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a given control-dominated data flow graph. We discuss delay and power issues with scheduling, and propose an improvement algorithm for insertion of so-called soft edges which enable power optimization under timing constraints. Power savings obtained by our approach on tested circuits range between 15 % and 30 % of the initial power dissipation},
   Keywords = {data flow graphs
digital integrated circuits
high level synthesis
optimisation
power supply circuits
scheduling
timing
control-dominated data flow graph
high-level synthesis
power consumption optimization
power dissipation
power management
power savings
power scheduling
power-efficient digital system design
scheduled delays
soft edge insertion
timing constraints},
   Year = {2002} }



@inproceedings{
hls:CCF03,
   Author = {Chen, Deming and Cong, J. and Fan, Yiping},
   Title = {Low-power high-level synthesis for FPGA architectures},
   BookTitle = { International Symposium on Low Power Electronics and Design },
   Pages = {134-139},
   Abstract = {This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estimator closely reflects both dynamic and static power contributed by various FPGA components in 0.1 /spl mu/m technology. The power estimation error is 16.2% on average. Second, we present a low power high level synthesis system, named LOPASS, for FPGA designs. It includes two algorithms for power consumption reduction: (i) a simulated annealing engine that carries out resource selection function unit binding, scheduling, register binding, and data pat. generation simultaneously to effectively reduce power; (ii) an enhanced weighted bipartite matching algorithm that is able to reduce the total amount of MUX ports by 22.7%. Experimental results show that LOPASS is able to reduce-power consumption by 35.8% compared to the results-of -Synopsys' Behavioral Compiler.},
   Keywords = {circuit CAD
field programmable gate arrays
high level synthesis
integrated circuit design
low-power electronics
network routing
simulated annealing
0.1 micron
FPGA architectures
LOPASS
RT-level power estimator
data path generation
dynamic power
enhanced weighted bipartite matching algorithm
function unit binding
low-power design
low-power high-level synthesis
power consumption reduction
register binding
resource selection
scheduling
simulated annealing engine
static power
wire length},
   Year = {2003} }



@inproceedings{
hls:CCF03,
   Author = {Chen, Deming and Cong, J. and Yiping, Fan},
   Title = {Low-power high-level synthesis for FPGA architectures},
   BookTitle = {  International Symposium on  Low Power Electronics and Design},
   Pages = {134-139},
   Abstract = {This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estimator closely reflects both dynamic and static power contributed by various FPGA components in 0.1 /spl mu/m technology. The power estimation error is 16.2% on average. Second, we present a low power high level synthesis system, named LOPASS, for FPGA designs. It includes two algorithms for power consumption reduction: (i) a simulated annealing engine that carries out resource selection function unit binding, scheduling, register binding, and data pat. generation simultaneously to effectively reduce power; (ii) an enhanced weighted bipartite matching algorithm that is able to reduce the total amount of MUX ports by 22.7%. Experimental results show that LOPASS is able to reduce-power consumption by 35.8% compared to the results-of -Synopsys' Behavioral Compiler.},
   Keywords = {circuit CAD
field programmable gate arrays
high level synthesis
integrated circuit design
low-power electronics
network routing
simulated annealing
0.1 micron
FPGA architectures
LOPASS
RT-level power estimator
data path generation
dynamic power
enhanced weighted bipartite matching algorithm
function unit binding
low-power design
low-power high-level synthesis
power consumption reduction
register binding
resource selection
scheduling
simulated annealing engine
static power
wire length},
   Year = {2003} }



@inproceedings{
hls:Dob01,
   Author = {Doboli, A.},
   Title = {Integrated hardware-software co-synthesis and high-level synthesis for design of embedded systems under power and latency constraints},
   BookTitle = {Design Automation and Test in Europe },
   Pages = {612-619},
   Abstract = {This paper presents an integrated approach to hardware software co-synthesis and HLS for design of low-power embedded systems. The main motivation for this work is that fine trade-offs between latency and power can be explored at the system level only with a detailed knowledge of used hardware resources. Integrated method was realized as a simulated annealing based solution-space exploration. Exploration is guided by Performance Models, that exactly capture the relationship between performances i.e. power consumption and latency and design decisions i.e. binding and scheduling. The proposed approach permits nor only a more accurate latency and power estimation but also the exposure of RTL-level design decisions at the system level. As a result, more effective power-latency trade-offs are possible during co-synthesis as compared to traditional task-level methods},
   Keywords = {hardware-software codesign
low-power electronics
scheduling
simulated annealing
HLS
Performance Models
RTL-level design decisions
binding
embedded systems
high-level synthesis
integrated hardware-software co-synthesis
latency constraints
low-power embedded systems
power estimation
scheduling
simulated annealing
solution-space exploration
used hardware resources},
   Year = {2001} }



@book{
hls-book3,
   Author = {Gajski, Daniel and Dutt, Nikil and Wu, Allen},
   Title = {High-Level Synthesis: Introduction to Chip and System Design},
   Publisher = {Kluwer Academic Publishers},
      Year = {1992} }



@inproceedings{
es:GVN+98,
   Author = {Gajski, D. D. and Vahid, F. and Narayan, S. and Jie, Gong},
   Title = {System-level exploration with SpecSyn},
   BookTitle = {Design Automation Conference},
   Pages = {812-817},
   Abstract = {We present the SpecSyn system-level design environment supporting the specify-explore-refine (SER) design paradigm. This three-step approach includes precise specification of system functionality, rapid exploration of numerous system-level design options, and refinement of the specification into one reflecting the chosen option. A system-level design option consists of an allocation of system, components like standard and custom processors, and a partitioning of functionality among those components. Focusing on SpecSyn's exploration techniques, we emphasize its two-phase estimation approach and highlight experiments using SpecSyn.},
   Keywords = {formal specification
high level synthesis
systems analysis
SpecSyn
system functionality
system-level design
system-level design environment
two-phase estimation},
   Year = {1998} }



@inproceedings{
hls:GOC94,
   Author = {Goodby, L. and Orailoglu, A. and Chau, P. M.},
   Title = {A high-level synthesis methodology for low-power VLSI design},
   BookTitle = { IEEE Symposium  Low Power Electronics },
   Pages = {48-49},
   Abstract = {A high-level synthesis methodology for low-power design is described. With the objective of supporting the design of low-power, performance-constrained systems such as signal processing applications, the methodology enables the designer to place throughput and latency constraints on the synthesized design. A library-based design style is used, where libraries may include multiple implementations of each component type. Library components are characterized by their relative power, area, and delay performance. The methodology has been implemented in the Sierra high-level synthesis system},
   Keywords = {high level synthesis
Sierra
area performance
delay performance
high-level synthesis methodology
latency constraints
library-based design style
low-power VLSI design
multiple implementations
performance-constrained systems
relative power
signal processing applications
throughput constraints},
   Year = {1994} }



@inproceedings{
hls:GYW+06,
   Author = {Gu, Zhenyu and Yonghong, Yang and Jia, Wang and Dick, R. P. and Li, Shang},
   Title = {TAPHS: thermal-aware unified physical-level and high-level synthesis},
   BookTitle = {Asia and South Pacific Design Automation Conference},
   Pages = {7 pp.},
   Abstract = {Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performance. It is necessary to consider thermal effects during all levels of the design process, from the architectural level to the physical level. However, design-time temperature prediction requires access to block placement, wire models, power profile, and a chip-package thermal model. Thermal-aware design and synthesis necessarily couple architectural-level design decisions (e.g., scheduling) with physical design (e.g., floorplanning) and modeling (e.g., wire and thermal modeling). This article proposes an efficient and accurate thermal-aware floor-planning high-level synthesis system that makes use of integrated high-level and physical-level thermal optimization techniques. Voltage islands are automatically generated via novel slack distribution and voltage partitioning algorithms in order to reduce the design's power consumption and peak temperature. A new thermal-aware floorplanning technique is proposed to balance chip thermal profile, thereby further reducing peak temperature. The proposed system was used to synthesize a number of benchmarks, yielding numerous designs that trade off peak temperature, integrated circuit area, and power consumption. The proposed techniques reduces peak temperature by 12.5/spl deg/C on average. When used to minimize peak temperature with a fixed area, peak temperature reductions are common. Under a constraint on peak temperature, integrated circuit area is reduced by 9.9% on average.},
   Keywords = {high level synthesis
integrated circuit layout
thermal management (packaging)
12.5 C
TAPHS
chip thermal profile
integrated high-level and physical-level thermal optimization
peak temperature
power consumption
slack distribution
thermal-aware unified physical-level and high-level synthesis
voltage island
voltage partitioning},
   Year = {2006} }



@article{
es:GSD+04,
   Author = {Gupta, S. and Savoiu, N. and Dutt, N. and Gupta, R. and Nicolau, A.},
   Title = {Using global code motions to improve the quality of results for high-level synthesis},
   Journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
   Volume = {23},
   Number = {2},
   Pages = {302-312},
   Note = {0278-0070},
   Abstract = {The quality of synthesis results for most high-level synthesis approaches is strongly affected by the choice of control flow (through conditions and loops) in the input description. This leads to a need for high-level and compiler transformations that overcome the effects of programming style on the quality of generated circuits. To address this issue, we have developed a set of speculative code-motion transformations that enable movement of operations through, beyond, and into conditionals with the objective of maximizing performance. We have implemented these code transformations, along with supporting code-motion techniques and variable renaming techniques, in a high-level synthesis research framework called Spark. Spark takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. We present results for experiments on designs derived from three real-life multimedia and image processing applications, namely, the MPEG-1 and -2 and GNU image manipulation program applications. We find that the speculative-code motions lead to reductions between 36% and 59% in the number of states in the finite-state machine (controller complexity) and the cycles on the longest path (performance) compared with the case when only nonspeculative code motions are employed. Also, logic synthesis results show fairly constant critical path lengths (clock period) and a marginal increase in area.},
   Keywords = {circuit optimisation
codes
embedded systems
hardware description languages
high level synthesis
image coding
parallelising compilers
ANSI-C
GNU
MPEG
Spark
circuit quality
clock period
code transformations
compiler transformation
control flow
controller complexity
critical path lengths
embedded systems
finite-state machine
global code motions
high-level synthesis
high-level transformation
image manipulation
image processing
input description
logic synthesis
longest path
parallelizing compilers
performance maximization
programmable circuits
real-life multimedia
register-transfer level VHDL
speculative-code motions
synthesis quality
variable renaming},
   Year = {2004} }



@inproceedings{
hls:HO93,
   Author = {Harris, I. G. and Orailoglu, A.},
   Title = {Intertwined scheduling, module selection and allocation in time-and-area constrained synthesis},
   BookTitle = {IEEE International Symposium on  Circuits and Systems },
   Pages = {1682-1685},
      Year = {1993} }



@inproceedings{
hls:HC99,
   Author = {Henning, R. and Chakrabarti, C.},
   Title = {Activity models for use in low power, high-level synthesis},
   BookTitle = { IEEE International Conference on  Acoustics, Speech, and Signal Processing },
   Volume = {4},
   Pages = {1881-1884 vol.4},
   Abstract = {Characteristics of the data being processed can be used to reduce the power consumption in the data path of a VLSI circuit by exploiting their relationship with transition activity during high-level synthesis. Important relationships between fixed-point, two's complement data characteristics and 0&rarr;1 transition activity in static CMOS circuits are presented in this paper. Models for computing transition activity in terms of a new set of transition parameters are developed. Propagation of data characteristics through multiplication and addition functional units is discussed. The use of the relationships and models to analyze and significantly reduce 0&rarr;1 transition activity with little computational effort is illustrated with examples},
   Keywords = {CMOS logic circuits
VLSI
adders
fixed point arithmetic
high level synthesis
integrated circuit modelling
multiplying circuits
semiconductor device models
VLSI circuit
activity models
addition functional unit
data characteristics propagation
data path
fixed-point data characteristics
high-level synthesis
low power synthesis
multiplication functional unit
power consumption reduction
transition activity
transition parameters
two's complement data characteristics},
   Year = {1999} }



@inproceedings{
hls:weilun05,
   Author = {W.L. Hung. and X. Wu and Y. Xie},
   Title = {Guaranteeing performance yield in high-level synthesis},
   BookTitle = {ICCAD},
      Year = {2006} }



@inproceedings{
hls:ID91,
   Author = {Ishikawa, M. and De Micheli, G.},
   Title = {A module selection algorithm for high-level synthesis},
   BookTitle = {IEEE International Sympoisum on  Circuits and Systems },
   Pages = {1777-1780 vol.3},
   Abstract = {A heuristic approach to the module selection problem in high-level synthesis is presented. In contrast to the common assumption made by most high-level synthesis systems, which consider one available resource for each type of operation, the authors assume that several resources with different delays and areas are available in a functional-block library. The proposed algorithm solves the scheduling, resource sharing, and module selection problems at the same time to achieve a circuit structure with near minimal area under a given overall latency constraint. Following the presentation of the algorithm, experimental results are reported},
   Keywords = {graph theory
logic CAD
scheduling
CAD
functional-block library
high-level synthesis
module selection algorithm
resource sharing
scheduling},
   Year = {1991} }



@inproceedings{
es:JPD95,
   Author = {Jha, P. and Parameswaran, S. and Dutt, N.},
   Title = {Reclocking for high level synthesis},
   BookTitle = {Asian and South Pacific Design Automation Conference },
   Pages = {49-54},
   Abstract = {Describes a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire delays of designs created by a high level synthesis system, and then finding an optimal clockwidth, we resynthesize the controller to improve performance without altering the datapath. Reclocking is versatile and can be applied not only for wire delay consideration, but also for bit-width migration, library migration and for feature size migration supporting the philosophy of design reuse. Experimental results show that with reclocking, the performance of the input designs can be improved by as much as 34%},
   Keywords = {high level synthesis
logic design
bit-width migration
feature size migration
high level synthesis
library migration
performance improvement
reclocking
wire delay consideration},
   Year = {1995} }



@article{
es:JD93,
   Author = {Jha, P. K. and Dutt, N. D.},
   Title = {Rapid estimation for parameterized components in high-level synthesis},
   Journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
   Volume = {1},
   Number = {3},
   Pages = {296-303},
   Note = {1063-8210},
   Abstract = {An important benefit of high-level synthesis is rapid design space exploration through examination of different design alternatives. However, such design space exploration is not feasible without fast and accurate area and delay estimates of the synthesized designs. These estimates must factor in physical design effects and technology-specific information in order to achieve accuracy. High-level synthesis tools often use abstract, parameterized component generators for describing the synthesized RT design, and thus need to be supported by fast and accurate estimators for these parameterized RT-components. Ideally, one would like to obtain the actual area and delay attributes of each component by constructing (or generating) the designs. However, such constructive methods require excessive run times, prohibiting on-line integration with the tasks of scheduling and allocation. This paper describes a fast (constant-time) method for estimating the area and delay of regular-structured generic RT components that are tuned to a particular technology library. The estimation models are generated using a least-square approximation on a set of sample data points from selected component implementations. The authors performed an extensive set of experiments to validate the estimation technique on combinational as well as sequential RT component generators. The results show a prediction of the area and delay to within 10% of the actual values. These models have also been integrated with a high-level synthesis system to permit on-line estimation of a component's area and delay},
   Keywords = {VLSI
circuit CAD
combinatorial circuits
integrated logic circuits
logic CAD
sequential circuits
area estimates
combinational RT component generators
delay estimates
high-level synthesis
least-square approximation
parameterized component generators
parameterized components
physical design effects
rapid design space exploration
regular-structured generic RT components
sample data points
sequential RT component generators
technology-specific information},
   Year = {1993} }

@inproceedings{
hls:KO92,
   Author = {Karri, R. and Orailoglu, A.},
   Title = {Transformation-based high-level synthesis of fault-tolerant ASICs},
   BookTitle = {Design Automation Conference},
   Pages = {662-665},
   Abstract = {The authors present a transformation-based approach to the high-level synthesis of fault-tolerant application-specific ICs (ASICs) satisfying a given performance constraint but requiring less than proportional increase in hardware over their nonredundant counterparts. They propose a synthesis methodology to exploit hardware minimizing transformations. A simple set of transformations are identified that minimize the fault-tolerance overhead. The selected transformations make the final design resilient to common mode failures. These transformations can be composed to form a rich set of complex transformations. An algorithm is presented to automatically identify structures in a flow graph where transformations can improve hardware utilization, and transformations that suit the structure best are applied. The system has been used to schedule several flow graphs},
   Keywords = {application specific integrated circuits
fault tolerant computing
logic CAD
common mode failures
fault-tolerance overhead
fault-tolerant ASICs
fault-tolerant application-specific ICs
flow graph
flow graphs
hardware minimizing transformations
hardware utilization
high-level synthesis
performance constraint},
   Year = {1992} }



@inproceedings{
hls:KO93,
   Author = {Karri, R. and Orailoglu, A.},
   Title = {High-Level Synthesis of Fault-Secure Microarchitectures},
   BookTitle = {Design Automation Conference},
   Pages = {429-433},
   Abstract = {Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip. A consequent increase in the number of on-chip faults as well as the growing import of quality metrics such as reliability and fault-tolerance are necessitating on-chip fault-tolerance. On-chip realization of a computation is fault-secure if no fault in the computation goes undetected. In this paper, we present high-level synthesis of fault-secure microarchitectures which require less than proportional increase in hardware. The proposed strategy selects intermediate computations for additional voting. The resulting class of fault-secure microarchitectures supplants the enormous hardware requirements of naive fault-secure strategies with enhanced hardware utilization afforded by securing the intermediate computations.},
      Year = {1993} }



@article{
hls:KO96,
   Author = {Karri, R. and Orailoglu, A.},
   Title = {Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors},
   Journal = {Reliability, IEEE Transactions on},
   Volume = {45},
   Number = {3},
   Pages = {404-412},
   Note = {0018-9529},
   Abstract = {Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip. A consequent increase in the number of on-chip faults as well as the growing importance of quality-metrics such as reliability and fault-tolerance are making on-chip fault-tolerance mandatory. On-chip realization of a computation is fault-secure if an observable error in the computation is detected. Components used in life-critical systems should be secured against all faults. While fault-security can be realized by duplicating the computation on disjoint hardware and voting on the result(s), such straightforward strategies entail appreciable hardware overhead. This paper presents computer-aided behavioral synthesis of fault-secure microarchitectures which require less than proportional increase in hardware. The strategy selects intermediate computations for additional voting. The resulting class of fault-secure microarchitectures supplants the enormous hardware requirements of naive fault-secure strategies with enhanced hardware utilization afforded by securing the intermediate computations. Experimental results show that fault-security can be implemented at a less than proportional increase in hardware overhead},
   Keywords = {VLSI
circuit CAD
digital signal processing chips
failure analysis
integrated circuit reliability
quality control
scheduling
additional voting
computer-aided behavioral synthesis
digital signal processors
fault-secure VLSI
fault-secure microarchitectures
high-level synthesis
intermediate computations
life-critical systems
on-chip fault-tolerance
on-chip faults
quality metrics
reliability
time-constrained scheduling},
   Year = {1996} }



@article{
hls:KJ01,
   Author = {Khouri, K. S. and Jha, N. K.},
   Title = {Clock selection for performance optimization of control-flow intensive behaviors},
   Journal = { IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems },
   Volume = {20},
   Number = {1},
   Pages = {158-165},
   Note = {0278-0070},
   Abstract = {This paper presents a clock selection algorithm for control-flow intensive behaviors that are characterized by the presence of conditionals and deeply nested loops. Unlike previous papers, which are primarily geared toward data-dominated behaviors, this algorithm examines the effects of branch probabilities and their interaction with allocation constraints. Using examples, we demonstrate, how changing branch probabilities and resource allocation can dramatically affect the optimal clock period, and hence, the performance of the schedule, and show that the interaction of these two factors must also be taken into account when searching for an optimal clock period. We then introduce the clock selection algorithm, which employs a fast critical-path analysis engine that allows it to evaluate what effect different clock periods, branch probabilities, and resource allocations may ultimately have on the performance of the behavior. When evaluating the critical path, we exploit the fact that our target behaviors exhibit locality of execution. We tested our algorithm using a number of benchmarks from various sources. A series of experiments demonstrates that our algorithm is quickly capable of selecting a small set of performance-enhancing clock periods, among which the optimal clock period typically lies. Another experiment demonstrates that the algorithm can adapt to varying resource constraints},
   Keywords = {circuit optimisation
clocks
critical path analysis
hardware description languages
high level synthesis
probability
resource allocation
scheduling
allocation constraints
branch probabilities
clock selection algorithm
control-flow intensive behaviors
critical-path analysis engine
deeply nested loops
locality of execution
optimal clock period
performance optimization
performance-enhancing clock periods
resource allocations},
   Year = {2001} }



@article{
hls:KLJ99,
   Author = {Khouri, K. S. and Lakshminarayana, G. and Jha, N. K.},
   Title = {High-level synthesis of low-power control-flow intensive circuits},
   Journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems },
   Volume = {18},
   Number = {12},
   Pages = {1715-1729},
   Note = {0278-0070},
   Abstract = {In this paper, we present a comprehensive high-level synthesis system that is geared toward reducing power consumption in control-flow intensive as well as data-dominated circuits. An iterative improvement framework allows the system to search the design space by examining the interaction between the different high-level synthesis tasks. In addition to incorporating traditional high-level synthesis tasks such as scheduling, module selection and resource sharing, we introduce a new optimization that performs power-conscious structuring of multiplexer networks, which are predominant in control-flow intensive circuits. The scheduler employed is capable of loop optimizations within and across loop boundaries. We also introduce a fast power estimation technique, based on switching activity matrices, to drive the synthesis process. Experimental results for a number of control-flow intensive and data-dominated benchmarks demonstrate power reduction of up to 62% (58%) when compared to V<sub>dd</sub>-scaled area-optimized (delay-optimized) designs. The area overheads over area-optimized designs are less than 39%, whereas the area savings over delay-optimized designs are up to 40%},
   Keywords = {circuit optimisation
high level synthesis
iterative methods
low-power electronics
scheduling
area overheads
data-dominated circuits
design space
high-level synthesis
iterative improvement framework
loop optimizations
low-power control-flow intensive circuits
module selection
multiplexer networks
power consumption
power-conscious structuring
scheduling
switching activity matrices},
   Year = {1999} }



@article{
hls:KK06,
   Author = {Krishnan, V. and Katkoori, S.},
   Title = {A genetic algorithm for the design space exploration of datapaths during high-level synthesis},
   Journal = {IEEE Transactions on Evolutionary Computation, },
   Volume = {10},
   Number = {3},
   Pages = {213-229},
   Note = {1089-778X},
   Abstract = {High-level synthesis is comprised of interdependent tasks such as scheduling, allocation, and module selection. For today's very large-scale integration (VLSI) designs, the cost of solving the combined scheduling, allocation, and module selection problem by exhaustive search is prohibitive. However, to meet design objectives, an extensive design space exploration is often critical to obtaining superior designs. We present a framework for efficient design space exploration during high-level synthesis of datapaths for data-dominated applications. The framework uses a genetic algorithm (GA) to concurrently perform scheduling and allocation with the aim of finding schedules and module combinations that lead to superior designs while considering user-specified latency and area constraints. The GA uses a multichromosome representation to encode datapath schedules and module allocations and efficient heuristics to minimize functional and storage area costs, while minimizing circuit latencies. The framework provides the flexibility to perform resource-constrained scheduling, time-constrained scheduling, or a combination of the two, using a simple and fast list-scheduling technique. A graded penalty function is used as an objective function in evaluating the quality of designs to enable the GA to quickly reach areas of the search space where designs meeting user specified criteria are most likely to be found. Since GAs are population-based search heuristics, a unique feature of our framework is its ability to offer a large number of alternative datapath designs, all of which meet design specifications but differ in module, register, and interconnect configurations. Many experiments on well-known benchmarks show the effectiveness of our approach.},
   Keywords = {VLSI
genetic algorithms
integrated circuit design
scheduling
search problems
allocation problem
combined scheduling problem
datapath schedule encoding
exhaustive search
extensive design space datapath exploration
genetic algorithm
high-level synthesis
list-scheduling technique
module allocations
module selection problem
multichromosome representation
penalty function
population based-search heuristics
resource-constrained scheduling
time-constrained scheduling
very large-scale integration designs
Datapath synthesis
design space exploration
genetic algorithms (GAs)
high-level synthesis},
   Year = {2006} }



@inproceedings{
hls:KSM+02,
   Author = {Kursun, E. and Srivastava, A. and Memik, S. G. and Sarrafzadeh, M.},
   Title = {Early evaluation techniques for low power binding},
   BookTitle = {International Symposium on  Low Power Electronics and Design },
   Pages = {160-165},
   Abstract = {This paper presents effective metrics to evaluate the power dissipation of scheduled data flow graphs (DFGs). This enables early evaluation of schedules without performing the computationally expensive resource-binding step. Our metrics correlate heavily (as high as 0.95 and > 0.75 for most test cases) with power dissipation values obtained after resource binding and rescheduling for power optimization steps. An experimental flow that integrates path-based scheduling, power optimal binding and power driven iterative rescheduling stages is constructed. The flow integrates commercial tools; like Synopsys, VSS and academic compilers like SUIF in a common optimization framework. Experimental results on DFGs from MediaBench suit also demonstrate the fact that metric evaluation is on average 42.6 times faster than performing optimal binding and iterative power improvement. Hence metric based evaluation enables fast design exploration at early stages.},
   Keywords = {circuit CAD
circuit optimisation
data flow graphs
high level synthesis
low-power electronics
processor scheduling
resource allocation
DFG metrics correlation
high level synthesis
iterative power improvement
low power binding early evaluation techniques
microarchitecture design
optimal binding
path-based scheduling
power dissipation values
power driven iterative rescheduling
power optimal binding
power optimization
resource binding/rescheduling
resource-binding step
schedule evaluation
scheduled data flow graph power dissipation},
   Year = {2002} }



@article{
hls:LS91,
   Author = {LEISERSON, C.E. and SAXE, J. B.},
   Title = {Retiming synchronous circuitry.},
   Journal = {Algorithmica},
   Volume = {6},
   Number = {1},
   Pages = {5-35.},
      Year = { 1991 } }



@inproceedings{
PV:LJ02,
   Author = {Lin, Zhong and Jha, N. K.},
   Title = {Interconnect-aware high-level synthesis for low power},
   BookTitle = {IEEE/ACM International Conference on Computer Aided Design},
   Pages = {110-117},
   Abstract = {Interconnects (wires, buffers, clock distribution networks, multiplexers and buses) consume a significant fraction of total circuit power. In this work, we demonstrate the importance of optimizing on-chip interconnects for power during high-level synthesis. We present a methodology to integrate interconnect power optimization into high-level synthesis. Our binding algorithm not only reduces power consumption in functional units and registers in the resultant register-transfer level (RTL) architecture, but also optimizes interconnects for power. We take physical design information into account for this purpose. To estimate interconnect power consumption accurately for deep sub-micron (DSM) technologies, wire coupling capacitance is taken into. consideration. We observed that there is significant spurious (i.e., unnecessary) switching activity in the interconnects and propose techniques to reduce it. Compared to interconnect-unaware power-optimized circuits, our experimental results show that interconnect power can be reduced by 53.1% on an average, while reducing overall power by an average of 26.8% with 0.5% area overhead. Compared to area-optimized circuits, the interconnect power reduction is 72.9% and overall power reduction is 56.0% with 44.4% area overhead.},
   Keywords = {capacitance
circuit layout CAD
circuit optimisation
high level synthesis
integrated circuit interconnections
integrated circuit layout
low-power electronics
DSM technologies
RTL architecture
binding algorithm
deep submicron technologies
interconnect power optimization
interconnect-aware high-level synthesis
on-chip interconnect optimization
power consumption
register-transfer level architecture
wire coup ling capacitance},
   Year = {2002} }



@article{
hls:LJ05,
   Author = {Lin, Zhong and Jha, N. K.},
   Title = {Interconnect-aware low-power high-level synthesis},
   Journal = { IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems },
   Volume = {24},
   Number = {3},
   Pages = {336-351},
   Note = {0278-0070},
   Abstract = {Interconnects (wires, buffers, clock distribution networks, multiplexers, and busses) consume a significant fraction of total circuit power. In this paper, we demonstrate the importance of optimizing on-chip interconnects for power during high-level synthesis. We present a methodology to integrate interconnect power optimization into high-level synthesis. It not only reduces datapath unit power consumption in the resultant register-transfer level architecture, but also optimizes interconnects for power. We take into account physical design information and coupling capacitance to estimate interconnect power consumption accurately for deep submicron technologies. We show that there is significant spurious (i.e., unnecessary) switching activity in the interconnects and propose techniques to reduce it. Compared with interconnect-unaware power-optimized circuits, interconnect power can be reduced by 53.1% on average, while overall power is reduced by an average of 26.8%, with negligible area overhead. Compared with area-optimized circuits, the interconnect power reduction is 72.9% and overall power reduction is 56.0%, with 44.4% area overhead. The power reductions are obtained solely through switched capacitance reduction (no voltage scaling is assumed).},
   Keywords = {capacitance
circuit optimisation
high level synthesis
integrated circuit interconnections
power consumption
area-optimized circuits
buffers
circuit power
clock distribution networks
coupling capacitance
datapath unit
interconnect power optimization
interconnect power reduction
low-power high-level synthesis
multiplexers
on-chip interconnects
power consumption
register-transfer level architecture
sub-micron technologies
switched capacitance reduction
switching activity
High-level synthesis
interconnect
low power},
   Year = {2005} }



@article{
hls:LM93,
   Author = {Ly, T. A. and Mowchenko, J. T.},
   Title = {Applying simulated evolution to high level synthesis},
   Journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
   Volume = {12},
   Number = {3},
   Pages = {389-409},
   Note = {0278-0070},
   Abstract = {A general optimization algorithm known as simulated evolution (SE) is applied to the tasks of scheduling and allocation in high level synthesis. Basically, SE-based synthesis explores the design space by repeatedly ripping up parts of a design in a probabilistic manner and reconstructing them using application-specific heuristics that combine rapid design iterations and probabilistic hill climbing to achieve effective design space exploration. Benchmark results are presented to demonstrate the effectiveness of this approach. The results of a number of experiments that provide insight into why SE-based synthesis works so well are given},
   Keywords = {circuit layout CAD
logic CAD
optimisation
scheduling
CAD
allocation
application-specific heuristics
design space exploration
high level synthesis
optimization algorithm
probabilistic hill climbing
rapid design iterations
scheduling
simulated evolution},
   Year = {1993} }



@article{
hls:LK03,
   Author = {Lyuh, Chun-Gi and Kim, Taewhan},
   Title = {High-level synthesis for low power based on network flow method},
   Journal = { IEEE Transactions on Very Large Scale Integration (VLSI) Systems },
   Volume = {11},
   Number = {3},
   Pages = {364-375},
   Note = {1063-8210},
   Abstract = {We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems for power optimization can be formulated as network flow problems and cand be solved optimally. However, in these formulations, a fixed schedule was assumed. In such a context, one key problem is that given an optimal network flow solution to a hardware allocation/binding problem for a given schedule, how to generate a new optimal network-flow solution rapidly for a local change of the given schedule. To this end, from a comprehensive analysis of the relation between network structure and flow computation, we devise a two-step procedure: Step 1) a max-flow computation step which finds a valid (maximum) flow solution while retaining the previous (maximum flow of minimum cost) solution as much as possible and Step 2) a min-cost computation step which incrementally refines the flow solution obtained in Step 1, using the concept of finding a negative cost cycle in the residual graph for the flow. The proposed algorithm can be applied effectively to several important high-level optimization problems (e.g., allocations/bindings of functional units, registers, buses, and memory ports) when we have the freedom to choose a schedule that will minimize power consumption. Experimental results (for bus synthesis) on benchmark problems show that our designs are 4%-40% more power-efficient over the designs produced by a random-move based solution and a clock-step based optimal solution, which is due to a) exploitation of the effect of scheduling and b) optimal binding for every schedule instance. Furthermore, our algorithm is about 2.6 times faster in run time over the full network flow based (optimal) algorithm, which is due to c) our novel (two-step) mechanism which utilizes the previous flow solution to reduce redundant flow computations.},
   Keywords = {data flow graphs
high level synthesis
low-power electronics
optimisation
scheduling
behavioral synthesis
hardware allocation
hardware binding
high-level synthesis
low power design
max-flow computation step
min-cost computation step
network flow method
power optimization algorithm
residual graph
scheduling},
   Year = {2003} }



@inproceedings{
hls:MSK+02,
   Author = {Memik, S. O. and Srivastava, A. and Kursun, E. and Sarrafzadeh, M.},
   Title = {Algorithmic aspects of uncertainty driven scheduling},
   BookTitle = {IEEE International Symposium on  Circuits and Systems },
   Volume = {3},
   Pages = {763-766},
   Abstract = {In this paper we discuss the algorithmic aspects of uncertainty driven scheduling which is a new design paradigm. Slack oriented design flow could be used to address the uncertainty problem in high level synthesis. We formalize the concept of slack and discuss different variations of the slack driven scheduling problem. The complexity issues are studied in detail and algorithms are proposed to solve the problem. These algorithms and proofs heavily exploit the concepts and techniques of graph theory and combinatorial optimization problems},
   Keywords = {DFG
NP-complete problem
VLSI
VLSI design
algorithmic aspects
automated design
circuit CAD
circuit optimisation
combinatorial optimization problems
complexity issues
computational complexity
data flow graph
data flow graphs
design paradigm
graph theory
high level synthesis
integrated circuit design
resource constrained scheduling
resource unconstrained scheduling
scheduling
slack oriented design flow
uncertainty driven scheduling
DFG
NP-complete problem
VLSI
VLSI design
algorithmic aspects
automated design
circuit CAD
circuit optimisation
combinatorial optimization problems
complexity issues
computational complexity
data flow graph
data flow graphs
design paradigm
graph theory
high level synthesis
integrated circuit design
resource constrained scheduling
resource unconstrained scheduling
scheduling
slack oriented design flow
uncertainty driven scheduling},
   Year = {2002} }



@inproceedings{
hls:MMM05,
   Author = {Mukherjee, R. and Memik, S. O. and Memik, G.},
   Title = {Peak temperature control and leakage reduction during binding in high level synthesis},
   BookTitle = {International Symposium on Low Power Electronic Devices},
   Pages = {251-256},
   Keywords = {application specific integrated circuits
high level synthesis
integrated circuit design
power consumption
temperature control
12.21 C
130 nm
ASIC design
HotSpot
functional unit
high level synthesis algorithm
leakage power
leakage reduction
lower level physical phenomenon
switching optimal binding solution
temperature aware binding algorithm
temperature control
temperature modeling tool},
   Year = {2005} }



@inproceedings{
PV:MOM05,
   Author = {Mukherjee, R. and Ogrenci Memik, S. and Memik, G.},
   Title = {Temperature-aware resource allocation and binding in high-level synthesis},
   BookTitle = {Design Automation Conference},
   Pages = {196-201},
   Abstract = {Physical phenomena such as temperature have an increasingly important role in performance and reliability of modern process technologies. This trend will only strengthen with future generations. Attempts to minimize the design effort required for reaching closure in reliability and performance constraints are agreeing on the fact that higher levels of design abstractions need to be made aware of lower level physical phenomena. In this paper, we investigated techniques to incorporate temperature-awareness into high-level synthesis. Specifically, we developed two temperature-aware resource allocation and binding algorithms that aim to minimize the maximum temperature that can be reached by a resource in a design. Such a control scheme will have an impact on the prevention of hot spots, which in turn is one of the major hurdles in front of reliability for future integrated circuits. Our algorithms are able to reduce the maximum attained temperature by any module in a design by up to 19.6/spl deg/C compared to a binding that optimizes switching power.},
   Keywords = {circuit optimisation
high level synthesis
integrated circuit design
integrated circuit reliability
logic design
resource allocation
binding algorithms
future integrated circuits reliability
high-level synthesis
intergrated circuit reliability
maximum temperature minimization
performance constraints
switching power optimization
temperature-aware resource allocation},
   Year = {2005} }



@article{
hls:PK89,
   Author = {Paulin, P. G. and Knight, J. P.},
   Title = {Force-directed scheduling for the behavioral synthesis of ASICs},
   Journal = { IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems },
   Volume = {8},
   Number = {6},
   Pages = {661-679},
   Note = {0278-0070},
   Abstract = {A general scheduling methodology is presented that can be integrated into specialized or general-purpose high-level synthesis systems. An initial version of the force-directed scheduling algorithm at the heart of this methodology was originally presented by the authors in 1987. The latest implementation of the logarithm introduced here reduces the number of functional units, storage units, and buses required by balancing the concurrency of operations assigned to them. The algorithm supports a comprehensive set of constraint types and scheduling modes. These include multicycle and chained operations; mutually exclusive operations; scheduling under fixed global timing constraints with minimization of functional unit costs, minimization of register costs, and minimization of global interconnect requirements; scheduling with local time constraints (on operation pairs); scheduling under fixed hardware resource constraints; functional pipelining; and structural pipeline (use of pipeline functional units). Examples from current literature, one of which was chosen as a benchmark for the 1988 High-Level Synthesis Workshop, are used to illustrate the effectiveness of the approach},
   Keywords = {application specific integrated circuits
circuit CAD
digital integrated circuits
integrated circuit technology
minimisation
pipeline processing
scheduling
ASIC
CAD
behavioral synthesis
chained operations
computer aided design
digital IC
fixed global timing constraints
fixed hardware resource constraints
force-directed scheduling algorithm
functional pipelining
functional unit costs
general scheduling methodology
global interconnect requirements
high-level synthesis systems
local time constraints
minimization
multicycle operations
mutually exclusive operations
register costs
structural pipeline},
   Year = {1989} }



@book{
hls-book2,
   Author = {Raghunathan, A. and Jha, N. K. and Dey, S.},
   Title = {High-Level Power Analysis and Optimization},
   Publisher = {Kluwer Academic Publishers},
      Year = {1998} }



@inproceedings{
PV:RRL00,
   Author = {Raghunathan, V. and Ravi, S. and Lakshminarayana, G.},
   Title = {High-level synthesis with variable-latency components},
   BookTitle = {International Conference on VLSI Design},
   Pages = {220-227},
   Abstract = {This paper presents techniques to integrate the use of variable latency units in a high-level synthesis design methodology. Components used as building blocks (e.g., functional units) in conventional high-level synthesis techniques are assumed to have fixed latency values. Variable latency units exhibit the property that the number of cycles taken to compute their outputs varies depending on the input values. While variable latency units offer potential for performance improvement, we demonstrate that realization of this potential requires that high-level synthesis be adapted suitably (sub-optimal use of variable latency units can lead to performance degradation, or unnecessarily high area overheads). Our techniques to incorporate variable latency units into high-level synthesis ensure that the performance improvement is maximized, while minimizing area overheads or satisfying resource constraints. These techniques do not assume specific high-level synthesis tools/algorithms, and can be plugged in to any generic high-level synthesis system. Since area overheads may still be incurred due to the use of variable latency units, we present a novel technique, based on the concept of reduced variable latency units, to further reduce area overheads. Reduced variable latency-units only implement the low latency case behavior of complete variable latency units. The use of reduced variable latency units significantly reduces area overheads, and frequently results in RTL implementations with simultaneous area and performance improvements compared to fixed latency implementations. Experimental results show that designs optimized using the proposed techniques achieve significant performance improvements (upto 1.6 X) over designs synthesized by a state-of-the-art high level synthesis tool, frequently with simultaneous improvements in area (upto 17.9%). In addition, while we do not explicitly target power reduction, we found the variable latency optimized designs to consume 35.7% less power on the average},
   Keywords = {VLSI
application specific integrated circuits
circuit optimisation
high level synthesis
integrated circuit design
low-power electronics
ASIC design
VLSI
area overheads
design optimization
fixed latency values
functional units
high-level synthesis
input values
performance degradation
power reduction
resource constraints
variable-latency components},
   Year = {2000} }



@article{
hls:ST94,
   Author = {Springer, D. L. and Thomas, D. E.},
   Title = {Exploiting the special structure of conflict and compatibility graphs in high-level synthesis},
   Journal = { IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
   Volume = {13},
   Number = {7},
   Pages = {843-856},
   Note = {0278-0070},
   Abstract = {Coloring of conflict graphs and clique partitioning of compatibility graphs have been used in high-level synthesis to map operators, values, and data transfers onto shared resources. However, finding a minimum sized coloring or clique partition is NP hard. One method to overcome this complexity is to identify special types of graphs that can be colored or clique partitioned in polynomial time. Existing high-level synthesis systems have exploited two special types of conflict graphs-interval and circular-arc graphs. However, they have provided no insight into why and how frequently these graphs occur. This paper will investigate the features of behavioral representations and synthesis algorithms that give rise to special conflict and compatibility graphs. We will identify two additional types of graphs useful for high-level synthesis-chordal and comparability graphs-and demonstrate their use in an existing high-level synthesis system},
   Keywords = {computational complexity
graph colouring
graph theory
logic CAD
polynomials
specification languages
NP hard
behavioral representations
chordal graphs
circular-arc graphs
clique partitioning
comparability graphs
compatibility graphs
conflict graphs
graph coloring
hardware description languages
high-level synthesis
interval graphs
polynomial time
shared resources
synthesis algorithms},
   Year = {1994} }



@article{
hls:SMC+05,
   Author = {Srivastava, A. and Memik, S. O. and Bo Kyung, Choi and Sarrafzadeh, M.},
   Title = {On effective slack management in postscheduling phase},
   Journal = { IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems },
   Volume = {24},
   Number = {4},
   Pages = {645-653},
   Note = {0278-0070},
   Abstract = {In this paper, we propose techniques for effective slack management in high-level synthesis. Our design methodology improves the usability of slack. This manifests itself in the form of relaxed latency constraints on resources. Relaxed latency constraints could be exploited to generate designs with better power, area, routability, and other measures. The slack-management engine has two key components: delay budgeting and resource binding. We propose a left edge traversal-based algorithm for delay budgeting. For resource binding, we developed an algorithm that applies a locally optimal binding procedure at each clock step. In order to demonstrate the effectiveness of our strategy, we built an experimental flow that integrated SUIF, Synopsys Design Compiler, Cadence Silicon Ensemble, and our own optimization tools. Experiments with the MediaBench suite shows that our methodology could generate designs with better quality than designs and faster design closure when compared with designs generated without slack management.},
   Keywords = {delays
high level synthesis
integrated circuit design
processor scheduling
resource allocation
delay budgeting
design closure
high-level synthesis
left edge traversal-based algorithm
optimal binding
postscheduling phase
relaxed latency constraints
resource binding
slack management
Design closure
high-level synthesis
slack management},
   Year = {2005} }



@inproceedings{
hls:TZB05,
   Author = {Tang, Xiaoyong and Zhou, Hai and Banerjee, P.},
   Title = {Leakage power optimization with dual-Vth library in high-level synthesis},
   BookTitle = {Design automation conference},
   Pages = {202-207},
   Abstract = {In this paper we address the problem of module selection during high-level synthesis. We present a heuristic algorithm for leakage power optimization based on the maximum weight independent set problem. A dual threshold voltage (V/sub th/) technique is used to reduce leakage energy consumption in a data flow graph. Experiments are performed on a data-path dominated test suite of six benchmarks. Our approach achieves an average of 70.9% leakage power reduction, which is very close to the optimal results from an integer linear programming approach.},
   Keywords = {circuit analysis computing
circuit optimisation
data flow graphs
high level synthesis
integer programming
leakage currents
linear programming
data flow graph
dual threshold voltage
dual-V/sub th/ library
heuristic algorithm
high-level synthesis
integer linear programming approach
leakage energy consumption
leakage power optimization
leakage power reduction
maximum weight independent set problem
module selection},
   Year = {2005} }



@inproceedings{
es:TIY98,
   Author = {Tomiyama, H. and Inoue, A. and Yasuura, H.},
   Title = {Statistical performance-driven module binding in high-level synthesis},
   BookTitle = {11th International Symposium on System Synthesis},
   Pages = {66-71},
   Abstract = {The inevitable fluctuation in fabrication processes results in LSI chips with various critical path delay even though all the chips are fabricated from the same design. Therefore, in LSI design, it is important to estimate what percentage of the fabricated chips will achieve the performance level and to maximize the percentage. This paper presents a model and a method to analyze statistical delay of RT-level datapath designs. The method predicts the probability that the fabricated circuits will work at a user specified clock period. Using the method, we can estimate a tight bound on the worst case critical path delay of the circuits. Based on the delay analysis method, a high-level module binding algorithm which maximizes the probability is also proposed. Experimental results demonstrate that the proposed statistical delay analysis method leads to lower-cost or higher-performance designs than conventional delay analysis methods},
   Keywords = {high level synthesis
integrated circuit design
integrated logic circuits
large scale integration
LSI design
RT-level datapath designs
delay analysis
high-level synthesis
module binding
statistical delay
tight bound
worst case critical path delay},
   Year = {1998} }



@inproceedings{
hls:Tosun05,
   Author = {Tosun, S. and Ozturk, O. and et al.},
   Title = {An {ILP} formulation for reliability-oriented high-level synthesis},
   BookTitle = { ISQED},
   Pages = {364-369},
   Keywords = {VLSI
adders
high level synthesis
integer programming
integrated circuit design
integrated circuit reliability
linear programming
ILP formulation
VLSI
adders
design quality
integer linear programming
multipliers
reliability-oriented high-level synthesis
soft error problem},
   Year = {2005} }



@inproceedings{
hls:shiue00,
   Author = {Shiue, W.},
   Title = {High level synthesis for peak power minimization using {ILP}},
   BookTitle = {ASAP},
   Keywords = {circuit CAD
circuit optimisation
data flow graphs
high level synthesis
integer programming
integrated circuit design
linear programming
low-power electronics
minimisation
pipeline arithmetic
scheduling
timing
DFG scheduling
HLS
ILP model
behavioral level power optimization
data-flow grap
heuristic-based algorithms
high level synthesis
integer linear program model
integer linear programming method
latency constraints
modified force-directed scheduling
multi-cycle arithmetic components
peak power minimization
pipelined arithmetic components
pipelining
timing constraints},
   Year = {2000} }



@inproceedings{
hls:ZKC05,
   Author = {Wo, Zhaojun and Koren, I. and Ciesielski, M.},
   Title = {An {ILP} formulation for yield-driven architectural synthesis},
   BookTitle = {International Symposium on  Defect and Fault Tolerance},
   Pages = {12-20},
   Abstract = {Data flow graph dominant designs, such as communication video and audio applications, are common in today's IC industry. In these designs, the datapath resources (e.g., adders, multipliers) count more than 90% in area. Different datapath resources have very different properties in terms of area, delay, power and yield. Considering yield during system level design can result in significant benefits. A mixed integer linear programming (MILP) formulation for yield-aware architectural synthesis is presented in this paper. The proposed approach attempts to maximize the yield of the design while satisfying other constraints like area and delay. Through experiments on several benchmarks, we show that incorporating the yield as an objective during architectural synthesis can significantly improve the yield compared to conventional methods. Transistor sizing at the circuit level can also be incorporated in our method to further improve the yield.},
   Keywords = {data flow graphs
integer programming
integrated circuit design
integrated circuit yield
linear programming
circuit level transistor sizing
data flow graphs
datapath resources
mixed integer linear programming
system level design
yield-driven architectural synthesis},
   Year = {2005} }



@inproceedings{
hls:CK02,
   Author = {Yoonseo, Choi and Taewhan, Kim},
   Title = {An efficient low-power binding algorithm in high-level synthesis},
   BookTitle = {IEEE International Symposium on  Circuits and Systems },
   Volume = {4},
   Pages = {IV-321-IV-324 vol.4},
   Abstract = {We propose an efficient binding algorithm for power optimization in high-level synthesis. In prior work, it has been shown that several binding problems for low-power can be formulated as multi-commodity flow problems (due to an iterative execution of data flow graph) and be solved optimally. However, since the multi-commodity flow problem is NP-hard, the application is limited to a class of small sized problems. To overcome the limitation, we address the problem of how we can effectively make use of the property of efficient flow computations in a network so that it is extensively applicable to practical designs while producing close-to-optimal results. To this end, we propose an efficient two-step algorithm, which (1) determines a feasible binding solution by partially utilizing the computation steps for finding a maximum flow of minimum cost in a network and then (2) refines it iteratively. Experiments with a set of benchmark examples show that the proposed algorithm saves the run time significantly while maintaining close-to-optimal bindings in most practical designs.},
   Keywords = {circuit optimisation
computational complexity
data flow graphs
high level synthesis
NP-hard
benchmark examples
close-to-optimal bindings
data flow graph
feasible binding solution
flow computations
high-level synthesis
low-power binding algorithm
multi-commodity flow problems
power optimization
two-step algorithm},
   Year = {2002} }
